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High-Accuracy, Dual-Axis Digital Inclinometer and Accelerometer ADIS16209
FEATURES
Dual-mode inclinometer system Dual-axis, horizontal operation, 90 Single-axis, vertical operation, 180 High accuracy, 0.1 14-bit digital inclination data, 0.025 resolution 14-bit digital acceleration data, 0.244 mg resolution 1.7 g accelerometer measurement range 12-bit digital temperature sensor output Digitally controlled bias calibration Digitally controlled sample rate Digitally controlled frequency response Dual alarm settings with rate/threshold limits Auxiliary digital I/O Digitally activated self-test Digitally activated low power mode SPI-compatible serial interface Auxiliary 12-bit ADC input and DAC output Single-supply operation: 3.0 V to 3.6 V 3500 g powered shock survivability
FUNCTIONAL BLOCK DIAGRAM
AUX ADC AUX DAC VREF
ADIS16209
TEMPERATURE SENSOR
DUAL-AXIS ACCELEROMETER
SIGNAL CONDITIONING AND CONVERSION
CALIBRATION AND DIGITAL PROCESSING
CS SCLK DIN DOUT
SPI PORT
SELF-TEST
DIGITAL CONTROL
VDD POWER MANAGEMENT ALARMS AUXILIARY I/O
GND
07096-001
RST
DIO1 DIO2
Figure 1.
APPLICATIONS
Platform control, stabilization, and alignment Tilt sensing, inclinometers, leveling Motion/position measurement Monitor/alarm devices (security, medical, safety) Navigation
GENERAL DESCRIPTION
The ADIS16209 is a high-accuracy, digital inclinometer that accommodates both single axis (180) and dual-axis (90) operation. The standard supply voltage (3.3 V) and serial peripheral interface (SPI) serial interface enable simple integration into most industrial system designs. A simple internal register structure handles all output data and configuration features. This includes access to the following output data: calibrated acceleration, accurate incline angles, power supply, internal temperature, auxiliary analog and digital input signals, diagnostic error flags, and programmable alarm conditions. Configurable operating parameters include sample rate, power management, digital filtering, auxiliary analog and digital output, offset/null adjustment, and self-test for sensor mechanical structure. The ADIS16209 is available in a 9.2 mm x 9.2 mm x 3.9 mm LGA package that operates over a temperature range of -40C to +125C. It can be attached using standard RoHS-compliant solder reflow processes.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADIS16209 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions..............................7 Recommended Pad Geometry ....................................................7 Typical Performance Characteristics ..............................................8 Theory of Operation ...................................................................... 10 Basic Operation .............................................................................. 11 Output Data Registers ............................................................... 12 Operation Control Registers ..................................................... 12 Calibration Registers .................................................................. 14 Alarm Registers .......................................................................... 14 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
3/08--Revison 0: Initial Version
Rev. 0 | Page 2 of 16
ADIS16209 SPECIFICATIONS
TA = 25C, VDD = 3.3 V, tilt = 0, unless otherwise noted. Table 1.
Parameter HORIZONTAL INCLINE Input Range Relative Accuracy Sensitivity VERTICAL ROTATION Input Range Relative Accuracy Sensitivity ACCELEROMETER Input Range 1 Nonlinearity1 Alignment Error Cross Axis Sensitivity Sensitivity ACCELEROMETER NOISE PERFORMANCE Output Noise Noise Density ACCELEROMETER FREQUENCY RESPONSE Sensor Bandwidth Sensor Resonant Frequency ACCELEROMETER SELF-TEST STATE 2 Output Change When Active TEMPERATURE SENSOR Output at 25C Scale Factor ADC INPUT Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Gain Error Input Range Input Capacitance ON-CHIP VOLTAGE REFERENCE Accuracy Reference Temperature Coefficient Output Impedance DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range Output Impedance Output Settling Time Conditions Each axis 30 from horizon, AVG_CNT = 0x08 30 from horizon Rotational plane within 30 degrees of vertical -180 360 of rotation -40C to +85C Each axis 25C % of full scale X sensor to Y sensor -40C to +85C, VDD = 3.0 V to 3.6 V AVG_CNT = 0x00 AVG_CNT = 0x00 0.25 0.025 1.7 0.1 0.1 2 0.244 1.7 0.19 50 5.5 At 25C 706 1343 1278 -0.47 12 2 1 4 2 0 During acquisition At 25C -10 40 70 5 k/100 pF to GND For Code 101 to Code 4095 12 4 1 5 0.5 0 to 2.5 2 10 Bits LSB LSB mV % V s 20 2.5 +10 2.5 1973 0.2 Min Typ 90 0.1 0.025 +180 Max Unit Degrees Degrees /LSB Degrees Degrees /LSB g % Degrees % mg/LSB mg rms mg/Hz rms Hz kHz LSB LSB C/LSB Bits LSB LSB LSB LSB V pF V mV ppm/oC
0.243
0.245
Rev. 0 | Page 3 of 16
ADIS16209
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input High Current, IINH Logic 0 Input Low Current, IINL All except RST RST 3 Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL SLEEP TIMER Timeout Period 4 START-UP TIME 5 Power-On Reset Recovery Sleep Mode Recovery FLASH MEMORY Endurance 6 Data Retention 7 CONVERSION RATE SETTING POWER SUPPLY Operating Voltage Range Power Supply Current Conditions Min 2.0 For CS signal when used to wake up from sleep mode VIH = 3.3 V VIL = 0 V 0.8 0.55 10 -60 Typ Max Unit V V V A A mA pF V V Seconds ms ms ms ms ms Cycles Years SPS V mA mA A
0.2 -40 -1 10
ISOURCE = 1.6 mA ISINK = 1.6 mA
2.4 0.4 0.5 128 150 190 30 70 2.5 20,000 20 1.04 3.0 3.3 11 36 140
Time until data is available Fast mode, SMPL_PRD 0x07 Normal mode, SMPL_PRD 0x08 Fast mode, SMPL_PRD 0x07 Normal mode, SMPL_PRD 0x08
TJ = 85C
2731 3.6 14 42 350
Normal mode, SMPL_PRD 0x08 Fast mode, SMPL_PRD 0x07 Sleep mode, -40C to +85C
1 2 3 4 5
Guaranteed by iMEMS(R) packaged part testing, design, and/or characterization. Self-test response changes as the square of VDD.
The RST pin has an internal pull-up.
Guaranteed by design.
The times presented in this section do not include the sensor's transient response time, which is associated with a 50 Hz single-pole system. System accuracy goals should be given consideration when determining the amount of time it takes to start acquiring accurate readings. These times do not include the time it takes to arrive at thermal stability, which can also introduce transient errors.
6 7
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at -40C, +25C, +85C, and +125C.
Retention lifetime equivalent at junction temperature (TJ) 55C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature.
Rev. 0 | Page 4 of 16
ADIS16209
TIMING SPECIFICATIONS
TA = 25C, VDD = 3.3 V, tilt = 0, unless otherwise noted. Table 2.
Parameter fSCLK tDATARATE tCS tDAV tDSU tDHD tDF tDR tSFS
1 2
Description Fast mode, SMPL_PRD 0x07 (fS 546 Hz)2 Normal mode, SMPL_PRD 0x08 (fS 482 Hz)2 Chip select period, fast mode, SMPL_PRD 0x07 (fS 546 Hz)2 Chip select period, normal mode, SMPL_PRD 0x08 (fS 482 Hz)2 Chip select to clock edge Data output valid after SCLK edge Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time Data output rise time CS high after SCLK edge
Min1 0.01 0.01 40 100 48.8 24.4 48.8
Typ
Max 2.5 1.0
100
5 5 5
12.5 12.5
Unit MHz MHz s s ns ns ns ns ns ns ns
Guaranteed by design, not tested. Note that fS means internal sample rate.
TIMING DIAGRAMS
tDATARATE tSTALL
CS
tSTALL = tDATARATE - 16/fSCLK
Figure 2. SPI Chip Select Timing
CS
tCS
SCLK 1 2 3 4 5 6 15 16
07096-002
SCLK
tSFS
tDAV
DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB
tDSU
DIN W/R A5
tDHD
A4 A3 A2 D2 D1 LSB
07096-003
Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
CS
DATA FRAME
SCLK
DIN
W/R
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5 DC4
DC3
DC2
DC1
DC0
WRITE = 1 READ = 0
REGISTER ADDRESS
DATA FOR WRITE COMMANDS DON'T CARE FOR READ COMMANDS
Figure 4. DIN Bit Sequence
Rev. 0 | Page 5 of 16
07096-004
ADIS16209 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Acceleration (Any Axis, Unpowered) Acceleration (Any Axis, Powered) VDD to GND Digital Input/Output Voltage to GND Analog Inputs to GND Analog Inputs to GND Operating Temperature Range Storage Temperature Range Rating 3500 g 3500 g -0.3 V to +7.0 V -0.3 V to +5.5 V -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V -40C to +125C -65C to +150C
THERMAL RESISTANCE
Table 4. Package Characteristics
Package Type 16-Terminal LGA JA 250C/W JC 25C/W Device Weight 0.6 grams
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 6 of 16
ADIS16209 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND VREF AUX ADC
16 15 14 13
AY SCLK AUX DAC AX DOUT
2
PIN 1 INDICATOR
VDD
12
1
ADIS16209
TOP LOOK THROUGH VIEW (Not to Scale)
NC
DIN
10
8
11
NC
3
CS
RST
4
5
6
7
DIO1
DIO2
NC
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5, 6 7, 8, 10, 11 9 12 13 14 15 16
1
Mnemonic SCLK DOUT DIN CS DIO1, DIO2 NC RST AUX DAC VDD AUX ADC VREF GND
Type 1 I O I I I/O N/A I O S I O S
Description SPI, Serial Clock. SPI, Data Output. SPI, Data Input. SPI, Chip Select. Digital Input/Output Pins. No Connect. Reset, Active Low. Auxiliary DAC Output. Power Supply, 3.3 V. Auxiliary ADC Input. Precision Reference. Ground.
S = supply; O = output; I = input.
RECOMMENDED PAD GEOMETRY
2.6955 8x 4.1865 8x
0.670 12x 8.373 2x 5.391 4x
0.500 16x
07096-006
1.127 16x 9.2mm x 9.2mm STACKED LGA PACKAGE
Figure 6. Example of a Pad Layout
Rev. 0 | Page 7 of 16
07096-005
NOTES 1. NC = NO CONNECT. 2. THIS IS NOT AN ACTUAL TOP VIEW, BECAUSE THE PINS ARE NOT VISIBLE FROM THE TOP. THIS IS A LAYOUT VIEW, WHICH REPRESENTS THE PIN CONFIGURATION, IF THE PACKAGE IS LOOKED THROUGH FROM THE TOP. THIS CONFIGURATION IS PROVIDED FOR PCB LAYOUT PURPOSES.
NC
9
ADIS16209 TYPICAL PERFORMANCE CHARACTERISTICS
0.20 0.15 0.10 0.10 MAXIMUM INCLINE ERROR 0.25 0.20 0.15
ERROR (Degrees)
0.05 0 -0.05 -0.10
ERROR (Degrees)
07096-018
0.05 0 -0.05 -0.10 -0.15
-0.15 -0.20 -40
-0.20 -30 -20 -10 0 10 20 30 40 0 100 200 300 400
07096-021
-0.25
INCLINATION ANGLE (Degrees)
ROTATIONAL ANGLE (Degrees)
Figure 7. Horizontal Inclination Error (8 Parts), Autonull at Horizontal Position, Stable Temperature, 3.3 V
0.3
Figure 10. Vertical Mode Rotational Error (8 parts), 25C, 3.3 V
0.3 0.2 0.1
0.2
ERROR (Degrees)
ERROR (Degrees)
0.1
0 -0.1 -0.2 -0.3
0
-0.1
-0.2
-0.4
07096-022
07096-019
-0.3 -60
-40
-20
0
20
40
60
80
100
-0.5 -60
-40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 8. Maximum Incline Error over a 30 Incline Range (8 Parts) over Temperature, Autonull at Horizontal Position, 25C, 3.3 V
0.15 0.10 0.05
ERROR (Degrees)
Figure 11. Vertical Mode Error (8 Parts) vs. Temperature, 0 to 360, 3.3 V
0.3 0.2 0.1
ERROR (Degrees)
0 -0.1 -0.2 -0.3 -0.4
0 -0.05 -0.10 -0.15 -0.20
07096-020
3.0
3.3 SUPPLY VOLTAGE (V)
3.6
3.0
3.3 SUPPLY VOLTAGE (V)
3.6
Figure 9. Maximum Incline Error over a 30 Incline Range (8 Parts) over Supply Voltage, Autonull Horizontal Position, 25C, 3.3 V
Figure 12. Vertical Mode Error (8 Parts) vs. Supply Voltage, 0 to 360, 25C
Rev. 0 | Page 8 of 16
07096-023
-0.5
ADIS16209
30 VDD = 3.0V, 3.3V, 3.6V TEMP = -40C, +25C, +85C
3.5 3.0 2.5
ERROR (Degrees)
PERCENTAGE OF POPULATION (%)
25
20
2.0 1.5 1.0
15
10
5
0.5 0
SENSITIVITY ERROR (%)
OFF-VERTICAL TILT (Degrees)
Figure 13. Accelerometer Output Sensitivity Error Distribution
20 18
PERCENTAGE OF POPULATION (%)
Figure 15. Error vs. Off-Vertical Tilt, 25C, 3.3 V
VDD = 3.0V, 3.3V, 3.6V TEMP = -40C, +25C, +85C
16 14 12 10 8 6 4 2 -6.0 -4.4 -2.8 -1.2 0.4 2.0 3.6 5.2
07096-014
0
BIAS ERROR (mg)
Figure 14. Accelerometer Output Bias Error Distribution
Rev. 0 | Page 9 of 16
07096-015
-0.38
-0.26
-0.14
-0.02
0.10
0.22
0.34
0.46
07096-013
0 -0.50
0
10
20
30
40
50
60
70
80
90
ADIS16209 THEORY OF OPERATION
The ADIS16209 tilt sensing system uses gravity as its only stimulus, and a MEMS accelerometer as its sensing element. MEMS accelerometers typically employ a tiny, spring-loaded structure that is interlaced with a fixed pick-off finger structure. The spring constant of the floating structure determines how far it moves when subjected to a force. This structure responds to dynamic forces associated with acceleration and to static forces, such as gravity. Figure 16 and Figure 17 illustrate how the accelerometer responds to gravity, according to its orientation, with respect to gravity. Figure 16 displays the configuration for the incline angle outputs, and Figure 17 displays the configuration used for the rotational angle position. This configuration provides greater measurement range than a single axis. The ADIS16209 incorporates the signal processing circuit that converts acceleration into an incline angle, and corrects for several known error sources that would otherwise degrade the accuracy level.
0 TILT LEVEL PLANE 13 12 4 5 89 POSITIVE X AXIS TILT DIRECTION 5 4 1 16 8 9 12 13
x GRAVITY = 1g
ax
x HORIZON
07096-007 07096-008
Figure 16. Single-Axis Tilt Theory Diagram
ay
x
GRAVITY = 1g
ax
x HORIZON
Figure 17. Dual-Axis Tilt Theory Diagram
1 16
1 X AXIS
16
13 12 8 9 X AXIS
4 Y AXIS 0 XINCL_OUT 90 YINCL_OUT = 0 Y AXIS
5 XINCL_OUT = 0 0 YINCL_OUT 90
07096-011
POSITIVE Y AXIS TILT DIRECTION
XINCL_OUT = 0 YINCL_OUT = 0
Figure 18. Horizontal Incline Angle Orientation
POSITIVE DIRECTION
1 6 20 9
16209
ROT_OUT = 0
90 ROT_OUT 180
-180 ROT_OUT -90
Figure 19. Vertical Angle Orientation
Rev. 0 | Page 10 of 16
07096-012
1 62 0 9
ADIS16209 BASIC OPERATION
The ADIS16209 requires only power/ground and SPI connections. The SPI is simple to hook up and is supported by many common digital hardware platforms. Figure 20 provides a simple hook-up diagram, while Table 2, Figure 2, and Figure 3 provide timing and bit assignments. Figure 4 provides the bit sequence for accessing the register memory structure. Each function within the ADIS16209 has its own 16-bit, 2-byte register. Each byte has its own unique, 6-bit address. Note that all 16 SCLK cycles are required for the DIN bit sequence to configure the output for the next data frame. The ADIS16209 supports full duplex mode operation. Table 6 provides the entire user register map for the ADIS16209. For each register, the lower bytes address is given. For those registers that have two bytes, the upper bytes address is simply the lower bytes address, incremented by 0x01. Table 6. User Register Map
Name ENDURANCE SUPPLY_OUT XACCL_OUT YACCL_OUT AUX_ADC TEMP_OUT XINCL_OUT YINCL_OUT ROT_OUT XACCL_NULL YACCL_NULL XINCL_NULL YINCL_NULL ROT_NULL ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL AUX_DAC GPIO_CTRL MSC_CTRL SMPL_PRD AVG_CNT SLP_CNT STATUS COMMAND R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R W Flash Backup Yes No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No Yes Yes Yes No No Address 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C to 0x1F 0x20 0x22 0x24 0x26 0x28 0x2A to 0x2F 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E Size (Bytes) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 2 2 2 2 6 2 2 2 2 2 2 2 2 Function Diagnostics, flash write counter (16-bit binary) Output, power supply Output, x-axis acceleration Output, y-axis acceleration Output, auxiliary ADC Output, temperature Output, 90 x-axis inclination Output, 90 y-axis inclination Output, 180 vertical rotational position Calibration, x-axis acceleration offset null Calibration, y-axis acceleration offset null Calibration, x-axis inclination offset null Calibration, y-axis inclination offset null Calibration, vertical rotation offset null Reserved, do not write to these locations Alarm 1, amplitude threshold Alarm 2, amplitude threshold Alarm 1, sample period Alarm 2, sample period Alarm, source control register Reserved Auxiliary DAC data Operation, digital I/O configuration and data Operation, data-ready and self-test control Operation, sample rate configuration Operation, filter configuration Operation, sleep mode control Diagnostics, system status register Operation, system command register Reference Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 16 Table 16 Table 17 Table 17 Table 17 Table 18 Table 18 Table 19 Table 19 Table 20 Table 14 Table 13 Table 12 Table 8 Table 10 Table 9 Table 21 Table 15
ADIS16209
CS SCLK DIN DOUT EMBEDDED PROCESSOR/ DSP/FPGA PF SCK MOSI MISO
07096-009
Figure 20. Typical SPI Hook-up
Many of the configuration registers have also been assigned mirror locations in the flash memory, which effectively provides them with a backup storage function. To assure the backup of these registers, the COMMAND register provides an initiation bit for manual flash updates. The ENDURANCE register provides a running count of these events.
Rev. 0 | Page 11 of 16
ADIS16209
OUTPUT DATA REGISTERS
Table 7 provides the data configuration for each output data register in the ADIS16209. Starting with the MSB of the upper byte, each output data register has the following bit sequence: new data (ND) flag, error/alarm (EA) flag, followed by 14 data bits. The data bits are LSB-justified and, in the case of the 12-bit data formats, the remaining two bits are not used. The ND flag indicates that unread data resides in the output data registers. This flag clears and returns to 0 during an output register read sequence. It returns to 1 after the next internal sample update cycle completes. The EA flag indicates an error condition. The STATUS register contains all of the error flags and provides the ability to investigate root cause. Table 7. Output Data Register Formats
Register SUPPLY_OUT XACCL_OUT YACCL_OUT AUX_ADC TEMP_OUT XINCL_OUT2 YINCL_OUT2 ROT_OUT3
1
of 68%. The two different modes of operation offer a systemlevel trade-off between performance (sample rate, serial transfer rate) and power dissipation.
Power Management
In addition to offering two different performance modes for power optimization, the ADIS16209 offers a programmable shutdown period that the SLP_CNT register controls. Table 9. SLP_CNT Bit Descriptions
Bit 15:8 7:0 Description Not used Data bits, 0.5 seconds/LSB (Default = 0x0000)
Bits 14 14 14 12 12 14 14 14
Format Binary, 3.3 V = 0x2A3D Twos complement Twos complement Binary, 2 V = 0x0CCC Binary, 25C = 0x04FE Twos complement Twos complement Twos complement
Scale1 0.30518 mV 0.24414 mg 0.24414 mg 0.6105 mV -0.47C 0.025 0.025 0.025
For example, writing 0x08 to the SLP_CNT register places the ADIS16209 into sleep mode for 4 seconds. The only way to stop this process is to remove power or reset the device.
Digital Filtering
The AVG_CNT register controls the moving average digital filter, which determines the size of the moving average filter, in eight power-of-two step sizes (that is, 2M = 1, 2, 4, 16, 32, 64, 128, and 256). Filter setup requires one simple step: write the appropriate M factor to the assigned bits in the AVG_CNT register. Table 10. AVG_CNT Bit Descriptions
Bit 15:4 3:0 Description (Default = 0x0004) Not used Power-of-two step size, maximum binary value = 1000
Scale denotes quantity per LSB. 2 Range is -90 to +90. 3 Range is -180 to +179.975.
OPERATION CONTROL REGISTERS
Internal Sample Rate
The SMPL_PRD register controls the ADIS16209 internal sample rate and has two parts: a selectable time base and a multiplier. The following relationship produces the sample rate: tS = tB x NS + 122.07s Table 8. SMPL_PRD Bit Descriptions
The following equation offers a frequency response relationship for this filter:
HA( f ) =
20 N=4 N = 128 MAGNITUDE (dB) -20 N = 16
sin( x N x f x t S ) N x sin( x f x t S )
0
Bit 15:8 7 6:0
Description Not used Time base (tB) 0 = 244.14 s, 1 = 7.568 ms Increment setting (NS)
(Default = 0x0004)
-40
An example calculation of the default sample period follows: SMPL_PRD = 0x01, B7 - B0 = 00000001 B7 = 0 tB = 244.14 s, B6...B0 = 000000001 NS = 1 tS = tB x NS + 122.07s = 244.14 x 1 + 122.07 = 366.21 s fS = 1tS = 2731 SPS The sample rate setting has a direct impact on the SPI data rate capability. For sample rates 546 SPS, the SPI SCLK can run at a rate up to 2.5 MHz. For sample rates <546 SPS, the SPI SCLK can run at a rate up to 1 MHz. The sample rate setting also affects power dissipation. When the sample rate is set to <546 SPS, power dissipation typically reduces by a factor
Rev. 0 | Page 12 of 16
-60
-80
0.01
0.1
f/fS
Figure 21. Frequency Response--Moving Average Filter
07096-010
-100 0.001
ADIS16209
Digital I/O Lines
The ADIS16209 provides two, general purpose, digital input/output lines that have several configuration options. Table 11. Digital I/O Line Configuration Registers
Function [Priority] Data-Ready I/O Indicator [1] Alarm Indicator [2] General-Purpose I/O Configuration [3] General-Purpose I/O Line Communication Register MSC_CTRL ALM_CTRL GPIO_CTRL GPIO_CTRL
Table 13. GPIO_CTRL Bit Descriptions
Bit 15:10 9 8 7:2 1 0 Description (Default = 0x0000) Not used General-Purpose I/O Line 2 data General-Purpose I/O Line 1 data Not used General-Purpose I/O Line 2, data direction control 1 = output, 0 = input General-Purpose I/O Line 1, data direction control 1 = output, 0 = input
Data-Ready I/O Indicator
The MSC_CTRL register provides controls for a data-ready function. For example, writing 0x05 to this register enables this function and establishes DIO2 as an active-low, data-ready line. The duty cycle is 25% (10% tolerance). Table 12. MSC_CTRL Bit Descriptions
Bit 15:11 10 9 8 7:3 2 1 0 Description (Default = 0x0000) Not used Self-test at power-on: 1 = disabled, 0 = enabled Not used Self-test enable (temporary, bit is volatile) 1 = enabled, 0 = disabled Not used Data-ready enable: 1 = enabled, 0 = disabled Data-ready polarity: 1 = active high, 0 = active low Data-ready line select: 1 = DIO2, 0 = DIO1
Auxiliary DAC
The auxiliary DAC provides a 12-bit level adjustment function. The AUX_DAC register controls the operation of the auxiliary DAC function, which is useful for systems that require analog level controls. It offers a rail-to-rail buffered output that has a range of 0 V to 2.5 V. The DAC can drive its output to within 5 mV of the ground reference when it is not sinking current. As the output approaches ground, the linearity begins to degrade (100 LSB beginning point). As the sink current increases, the nonlinear range increases. The DAC output latch function, contained in the COMMAND register, provides continuous operation while writing to each byte of this register. The contents of this register are volatile, which means that the desired output level must be set after every reset and power cycle event. Table 14. AUX_DAC Bit Descriptions
Bit 15:12 11:0 Description (Default = 0x0000) Not used Data bits, scale factor = 0.6105 mV/code Offset binary format, 0 V = 0 codes
Self-Test
Self-test exercises the mechanical structure of the sensor and provides a simple method for verifying the operation of the entire sensor signal conditioning circuit. There are two different self-test options: startup and manual. If either of these self-tests results in a failure, the self-test error flag, located in the STATUS register, sets to 1. The manual self-test option results in a repeating pattern, until the bit is set back to 0. While in the manual self-test loop, SMPL_PRD and AVG_CNT cannot be changed. See Table 12 for the appropriate MSC_CTRL bit designations.
Global Commands
The COMMAND register provides initiation bits for several commands that simplify many common operations. Writing a 1 to the assigned COMMAND bit exercises its function. Table 15. COMMAND Bit Descriptions
Bit 15:8 7 6:5 4 3 2 1 0 Description (Default = 0x0000) Not used Software reset Not used Clear status register (reset all bits to 0) Flash update; backs up all registers, see Table 6 DAC data latch Factory calibration restore Autonull
General Purpose I/O
The GPIO_CTRL register controls the direction and data of the general-purpose digital lines, DIO1 and DIO2. For example, writing a 0x02 to the GPIO_CTRL register sets DIO2 as an output line and DIO1 as an input line. Reading the data bits in GPIO_CTRL reveals the line logic level.
The software reset command restarts the internal processor, which loads all registers with the contents in their flash memory locations.
Rev. 0 | Page 13 of 16
ADIS16209
The flash update copies the contents of all the flash backup registers into their assigned, nonvolatile, flash memory locations. This process takes approximately 50 ms and requires a power supply that is within the specified operating range. After waiting the appropriate time for the flash update to complete, verify successful completion by reading the STATUS register (if successful, the flash update error is 0). If the flash update was not successful, reading this error bit accomplishes two things: (1) alerting the system processor to try again, and (2) clearing the error flag, which is required for flash memory access. The DAC data latch command loads the contents of AUX_DAC into the DAC latches. Because the AUX_DAC contents must be updated one byte at a time, this command ensures a stable DAC output voltage during updates. The autonull command provides a simple method for removing offset from the sensor outputs. This command takes the contents of the output data registers and loads the equal but opposite number into the offset calibration registers. The accuracy of this operation depends on zero force, zero motion, and optimal noise management during the measurement (see the Digital Filtering section). The factory calibration restore sets the offset null registers (XACCL_NULL, for example) back to their default values.
ALARM REGISTERS
The alarm function provides monitoring for two independent conditions. The ALM_CTRL register provides control inputs for data source, data filtering (prior to comparison), static/ dynamic, and output indicator configurations. The ALM_MAGx registers establish the trigger threshold and polarity configurations. The ALM_SMPLx registers provide the numbers of samples to use in the dynamic, rate-of-change configuration. The rate-of-change calculation is
YC = 1 N DS
N DS n =1
y (n + 1) - y (n) Alarm is YC > or < M C ?
where: NDS is the number of samples in ALM_SMPLx. y(n) is the sampled output data. MC is the magnitude for comparison in ALM_MAGx. > or < is determined by the MSB in ALM_MAGx. Table 18. ALM_MAG1/ALM_MAG2 Bit Designations
Bit 15 14 13:0 Description (Default = 0x0000) Comparison polarity: 1 = greater than, 0 = less than Not used Data bits, matches format of trigger source selection
CALIBRATION REGISTERS
The ADIS16209 incorporates an extensive factory calibration and provides precision acceleration, incline, and rotational position data. For systems that require on-site calibration, user-programmable offset adjustment registers are available. Table 16 provides the bit assignments for the following userprogrammable calibration registers: XACCL_NULL and YACCL_NULL. Table 17 provides the bit assignments for the following user-programmable calibration registers: XINCL_NULL, YINCL_NULL, and ROT_NULL. Table 16. Acceleration Offset Register Bit Designations
Bit 15:14 13:0 Description (Default = 0x0000) Not used Data bits, twos complement, sensitivity = 0.24414 mg/LSB
Table 19. ALM_SMPL1/ALM_SMPL2 Bit Designations
Bit 15:8 7:0 Description (Default = 0x0001) Not used Data bits: number of samples (both 0x00 and 0x01 = 1)
Table 20. ALM_CTRL Bit Descriptions
Bit 15:12 Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 11:8 7 6 5 4 3 2 1 0
1
Table 17. Incline/Rotation Offset Register Bit Designations
Bit 15:14 13:0 Description (Default = 0x0000) Not used Data bits, twos complement, sensitivity = 0.025/LSB
Description (Default = 0x0000) Trigger source, Alarm 2 Disabled Power supply X-acceleration Y-acceleration Auxiliary ADC Temperature sensor X-axis incline angle Y-axis incline angle Rotational position Trigger source, Alarm 1, same as Bits [15:12] Not used Alarm 2 rate of change control: 1 = enabled Alarm 1 rate of change control: 1 = enabled Alarm 2 filter: 1 = filtered data, 0 = no filter1 Alarm 1 filter: 1 = filtered data, 0 = no filter1 Alarm indicator, using DIO1/DIO2: 1 = enabled Alarm indicator polarity: 1 = active high Alarm indicator line select: 1 = DIO2, 0 = DIO1
Incline and vertical angles always use filtered data in this comparison.
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ADIS16209
Status
The STATUS register provides a series of error flags that provide indicator functions for common system-level issues. All of the flags clear (set to 0) after each STATUS register read cycle. If an error condition remains, the error flag returns to 1 during the next sample cycle. Table 21. STATUS Bit Descriptions
Bit 15:10 9 8 7:6 5 4 3 2 1 0 Description (Default = 0x0000) Not used Alarm 2 status: 1 = active, 0 = inactive Alarm 1 status 1 = active, 0 = inactive Not used Self-test diagnostic error flag 1 = error condition, 0 = normal operation Not used SPI communications failure 1 = error condition, 0 = normal operation Flash update failed 1 = error condition, 0 = normal operation Power supply above 3.625 V 1 3.625 V, 0 3.625 V (normal) Power supply below 2.975 V 1 2.975 V, 0 2.975 V (normal)
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ADIS16209 OUTLINE DIMENSIONS
9.35 MAX 2.6955 BSC (8x) 5.391 BSC (4x) PIN 1 INDICATOR 1.000 BSC (16x)
1
13 12
16
9.20 TYP
8.373 BSC (2x) 0.797 BSC (12x)
9 8 5 4
TOP VIEW
5.00 TYP
0.200 MIN (ALL SIDES)
BOTTOM VIEW
0.373 BSC (16x)
3.90 MAX
022007-B
SIDE VIEW
Figure 22. 16-Terminal Land Grid Array [LGA] (CC-16-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADIS16209CCCZ 1 ADIS16209/PCBZ1
1
Temperature Range -40C to +125C
Package Description 16-Terminal Land Grid Array [LGA] Evaluation Board
Package Option CC-16-2
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07096-0-3/08(0)
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